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Junction temperature and thermal resistance calculator

Power devices and thermal design. Everything is calculated in your browser; nothing you enter is sent to a server.

KEY POINTS

Junction temperature is Tj = Ta + P × (θjc + θcs + θsa); like electrical resistances, thermal resistances in series add up. The lifetime of power semiconductors depends strongly on Tj, so designs usually keep a 20 to 30 °C margin below Tj(max). This tool calculates Tj and works back to the allowable loss and required heat sink on one screen.

Junction temperature from thermal resistance

Power dissipation (loss) P (W)Ambient temperature Ta (°C)θjc (junction to case) (°C/W)θcs (case to heat sink, TIM) (°C/W)θsa (heat sink to ambient) (°C/W)Maximum junction temperature Tj(max) (°C)Design margin (°C)

Junction temperature Tj117.5°C

Case temperature Tc97.5°C

Heat sink temperature Ts90.0°C

Total thermal resistance θja3.10°C/W

Maximum loss that keeps Tj at or below 125 °C27.4W

Required heat sink thermal resistance θsa2.30°C/W or less

A steady-state series model. Evaluate pulsed switching losses and short heating events such as motor start-up with the transient thermal impedance Zth(j-c) curve in the datasheet.

Estimating from measured top-of-package temperature (ψjt)

Measured package top temperature Tt (°C)ψjt (thermal characterization parameter) (°C/W)

Estimated junction temperature Tj = Tt + P·ψjt97.5°C

ψjt is not a thermal resistance but the difference between top temperature and Tj divided by power. For surface-mount packages that shed most heat into the board, it suits measurement better than θjc. Power P is taken from the field above.

Loss and junction temperature

Calculated with θja = 3.10 °C/W and Ta = 40 °C.
Loss	Tj	Result
6.3 W	59.4 °C	OK
12.5 W	78.8 °C	OK
18.8 W	98.1 °C	OK
25.0 W	117.5 °C	OK
31.3 W	136.9 °C	Insufficient margin
37.5 W	156.3 °C	Exceeds rating

Typical thermal resistance by package

Typical ranges. Actual values vary widely with each device's datasheet and the mounting board (copper area, layer count).
Package	θja (°C/W)	θjc (°C/W)
SOT-23	About 200 to 300	— (heat flows mainly into the board)
SOIC-8	About 100 to 160	About 25 to 40
QFN 5×6 mm (power)	About 40 to 60 (board dependent)	About 1 to 3
D²PAK (TO-263)	About 40 to 60 (board dependent)	About 0.5 to 1.5
TO-220	About 60 to 65 (no heat sink)	About 0.5 to 2
TO-247	About 40 (no heat sink)	About 0.2 to 0.8
Power module (per device)	— (heat sink required)	About 0.05 to 0.3

Thinking in thermal resistance

Thermal resistance is the temperature difference produced by 1 W of heat flow. As with Ohm's law in electrical circuits, thermal resistances in series add up. Heat generated at the junction of a chip flows through the die, the solder or sintered layer, the heat spreader (case), the TIM, the heat sink and the air, and each stage has its own thermal resistance.

The lifetime of power semiconductors depends strongly on junction temperature; by the Arrhenius rule of thumb, lifetime roughly halves for every 10 °C rise. Designs therefore usually keep 20 to 30 °C of margin below Tj(max) rather than running right at the limit. SiC power devices can be rated at a Tj(max) of 175 to 200 °C, and the smaller heat sinks that allows are one of their advantages.

FAQ

What is the difference between θjc and ψjt?

θjc is a true thermal resistance measured with heat forced through the case. ψjt is a characterization parameter used to estimate Tj from the measured top-of-package temperature.

How much margin below Tj(max) is typical?

Designs commonly keep 20 to 30 °C of margin, because lifetime roughly halves for every 10 °C rise by the Arrhenius rule of thumb.

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Last updated: October 23, 2026