EOT and MOS capacitor (C–V) calculator
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KEY POINTS
EOT expresses capacitance as an equivalent SiO₂ thickness: EOT = t_IL + t_HK × 3.9/k_HK. Two nm of HfO₂ (k ≈ 20) on a 0.5 nm interfacial layer gives an EOT of about 0.9 nm. A high-k film is physically thick to limit leakage yet behaves electrically like a thin film. The interfacial SiO₂ layer does not shrink, so it sets the floor for EOT.
Inputs
The C-V curves are for an ideal MOS structure (no interface states or oxide charge, no gate depletion or quantum effects). Measured inversion capacitance is lower than Cox because of inversion layer quantization and polysilicon gate depletion, so the electrical thickness derived from it (CET) is 0.3 to 0.5 nm thicker than EOT.
C–V characteristics (p-type substrate, normalized C/Cox)
Physical thickness and EOT for HfO₂ (k ≈ 20) (IL 0.5 nm)
| High-k thickness | Total physical thickness | EOT | Cox |
|---|---|---|---|
| 0.5 nm | 1.0 nm | 0.598 nm | 5.779 µF/cm² |
| 1 nm | 1.5 nm | 0.695 nm | 4.969 µF/cm² |
| 1.5 nm | 2.0 nm | 0.792 nm | 4.357 µF/cm² |
| 2 nm | 2.5 nm | 0.890 nm | 3.880 µF/cm² |
| 3 nm | 3.5 nm | 1.085 nm | 3.183 µF/cm² |
| 5 nm | 5.5 nm | 1.475 nm | 2.341 µF/cm² |
Why high-k films lower EOT
Transistor drive current is proportional to gate capacitance Cox, so gate dielectrics were thinned with each generation. Once SiO₂ went below 2 nm, however, tunneling current made gate leakage soar and standby power became unacceptable. High-k technology uses materials with a higher dielectric constant, such as HfO₂, to make a film that is physically thick (low leakage) yet electrically thin (high capacitance). EOT expresses that capacitance as an equivalent SiO₂ thickness.
A thin SiO₂ interfacial layer (IL) of 0.3 to 1 nm is needed between the high-k film and silicon to preserve interface quality, and it sets the floor for EOT. Making the high-k film thicker does nothing to the IL, so leading-edge nodes keep EOT below 1 nm by thinning the IL (scavenging) in combination with high-k/metal gates.
FAQ
What is the difference between EOT and CET?
EOT is calculated from the dielectric stack alone. CET is the electrical thickness measured in inversion, which is 0.3 to 0.5 nm thicker because of inversion layer quantization and gate depletion.
Why does high-frequency capacitance stay low in inversion?
At high frequency the inversion layer cannot respond, so the depletion width stays at its maximum and capacitance stays at Cmin.
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Last updated: October 23, 2026