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Setup and hold timing slack calculator

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KEY POINTS

Setup slack is the clock period + skew − setup time − uncertainty − (tcq + combinational delay); if it is negative, lower the frequency or reduce the logic depth. Hold is a "too fast" problem where new data overtakes on the same edge. Lowering the frequency does not fix it; inserting delay buffers does.

Inputs (all times in ps)

Clock frequency (MHz)Clock-to-Q delay tcq (max)Clock-to-Q delay tcq (min)Combinational delay (longest path)Combinational delay (shortest path)Setup time tsetupHold time tholdClock skew (capture − launch)Uncertainty (jitter and margin, setup)Uncertainty (hold)

Setup slack30.0ps

Hold slack20.0ps

Clock period T500.0ps

Maximum frequency of this path2128MHz

Data arrival time (setup / hold)425 / 55ps

Rough number of 15 ps gates that fit27stages

Positive skew (the capture clock arrives later) helps setup and hurts hold. Real static timing analysis (STA) checks every path at each process, voltage and temperature corner, including wire parasitic RC and on-chip variation (OCV).

Frequency and setup slack

Frequency	Period	Setup slack	Result
1000 MHz	1000 ps	530 ps	OK
1500 MHz	667 ps	197 ps	OK
2000 MHz	500 ps	30 ps	OK
2500 MHz	400 ps	-70 ps	Violation
3000 MHz	333 ps	-137 ps	Violation
3500 MHz	286 ps	-184 ps	Violation

Setup versus hold

In a synchronous circuit, data launched from one flip-flop must reach the capturing flip-flop before the next clock edge (setup time) and stay stable for a while after the edge (hold time). Setup is a "too slow" problem: the logic is too long for the clock period, and lowering the frequency fixes it. Hold is a "too fast" problem: new data races through on the same edge, and it occurs regardless of frequency.

A single path with negative slack is enough to make a chip fail. Late in the design, slack is checked by static timing analysis using delays extracted after place and route, and violations are driven to zero through clock tree tuning and gate sizing before tape-out.

FAQ

Does clock skew help or hurt?

Positive skew, where the capture clock arrives later, gives setup more time but makes hold harder. Designers sometimes add skew on purpose (useful skew) to fix setup violations.

Why doesn't lowering the frequency fix hold violations?

Hold compares data and clock on the same edge, so the clock period does not appear in the hold check. Only adding delay on the short path fixes it.

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Last updated: October 23, 2026