3D NAND capacity and bit density calculator
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KEY POINTS
3D NAND capacity is vertical strings × layers × bits per cell, so it grows by adding layers or bits. Dies with 200-plus layers and TLC have reached around 15 Gb/mm². Moving from TLC to QLC multiplies capacity by 4/3, but doubling the threshold states narrows the window and reduces write speed and endurance.
Inputs
The defaults are set to match a 200-plus-layer, TLC, 1 Tb-class die (published bit densities around 15 Gb/mm²). Placing CMOS circuits under the array (CuA, CMOS under Array) or building them on a separate wafer and bonding it raises array efficiency substantially.
Layer count and bit density
Bits per cell and read margin
| Bits per cell | Threshold states | Vth window per state (share of total) | Capacity with this die structure |
|---|---|---|---|
| 1 bit | 2 | 100.0 % | 318 Gib |
| 2 bits | 4 | 33.3 % | 637 Gib |
| 3 bits | 8 | 14.3 % | 955 Gib |
| 4 bits | 16 | 6.7 % | 1274 Gib |
| 5 bits | 32 | 3.2 % | 1592 Gib |
3D NAND capacity grows with layers × bits
In planar NAND flash, shrinking cells made interference between neighbors and the dwindling number of stored electrons a problem, and scaling stopped around 15 nm. 3D NAND stacks hundreds of word line and insulator layers, drills vertical holes (channel holes) through them and builds cells along the hole walls, growing capacity with layer count while relaxing lateral dimensions.
The other lever is bits per cell: moving from TLC to QLC multiplies capacity by 4/3. The number of states doubles, though, narrowing the threshold voltage window and reducing write speed and endurance. High-aspect-ratio etching that drills deep holes in one pass, and deposition that stacks hundreds of films without wafer bow, are the main technical challenges in adding layers.
FAQ
How does QLC compare with TLC?
QLC stores 4 bits per cell instead of 3, giving 4/3 the capacity, but it needs 16 threshold states instead of 8, which lowers write speed and endurance.
What limits adding more layers?
Etching very deep, high-aspect-ratio channel holes in one pass and depositing hundreds of films without excessive wafer bow are the main challenges.
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Last updated: October 23, 2026