Transistor density (MTr/mm²) calculator
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KEY POINTS
Logic transistor density is often measured with a metric built from two cells, NAND2 and a scan flip-flop: 0.6 × (4 / NAND2 area) + 0.4 × (36 / SFF area). Density scales roughly inversely with CPP × metal pitch, and Intel 10nm dimensions (CPP 54 nm, MMP 36 nm) give about 100 MTr/mm². Comparing this density, not node names, is the fair comparison.
Transistor density from cell dimensions
The defaults are close to Intel 10nm's published dimensions (CPP 54 nm, MMP 36 nm, cell height about 272 nm) and give a result close to its published density of 100.8 MTr/mm². The average density of a real chip is much lower because it includes SRAM, analog, routing and unused area.
Extrapolating with Moore's law
Logic density of major processes
| Process | Density (MTr/mm²) | Type of source |
|---|---|---|
| Intel 14nm | 37.5 | Published by Intel |
| Intel 10nm (Intel 7) | 100.8 | Published by Intel |
| TSMC N7 | About 91 | Estimate from analysis |
| TSMC N5 | About 170 | Estimate from analysis |
| TSMC N3 | About 200 to 290 | Estimate (varies with cell library) |
Compare density, not node names
Node names such as "5nm" and "3nm" no longer describe any physical transistor dimension, so they cannot be compared across companies by the number alone. The metric proposed instead counts transistors per mm² from the areas of two representative cells, a NAND2 and a scan flip-flop. Density scales roughly inversely with CPP × MMP and also rises when the number of tracks in the cell height is reduced.
Shrinking CPP and MMP is approaching physical limits and density gains have slowed. The industry has entered a phase of structural design-technology co-optimization (DTCO): fewer fins to lower cell height, GAA nanosheets to cut tracks, backside power delivery to free front-side routing and CFETs that stack nMOS and pMOS vertically.
FAQ
Why don't node names match feature sizes?
Node names no longer describe any physical transistor dimension and differ between companies, so density is used for comparison instead.
Why is real chip density lower?
Chips also contain SRAM, analog blocks, routing and unused space, so the average density is well below the logic cell density.
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Last updated: October 23, 2026