T5230
A test system that uses a combined array architecture for cost-efficient wafer testing of NAND and other non-volatile memory.
Maker: Advantest · Official product page
Specifications
| Parallel testing | 1,536 devices |
|---|---|
| Target | NAND, non-volatile memory, wafer-level burn-in |
| Configuration | Connects to single or multi-wafer probers |
Specifications as published by the maker. See the sources below.
Overview
T5230 is Advantest's test system for non-volatile memory. It handles wafer testing and wafer burn-in of non-volatile memory devices including NAND flash.
Its combined array architecture fits any test cell layout and achieves very high cost efficiency in wafer tests such as wafer-level burn-in (WLBI) and built-in self-test (BIST). Several test cells connect to the system controller, and each cell can run wafer tests independently.
Test cells can connect to standard single-wafer probers or to one multi-wafer prober, and can also dock with probers in multi-unit, multi-level configurations. Faster data transfer shortens test time, and the OS is FutureSuite.
Key features
- Combined array architecture
- 1,536 devices tested at once
- Connects to many kinds of probers
Applications
- Wafer testing and WLBI of NAND
Other memory test systems
More from Advantest
- 7038 System-Level Test System · Final test equipment
- B6700 series · Burn-in systems
- EVA100 · Analog test systems
- EXAVIS · Power semiconductor manufacturing equipment
- HA1200 · Wafer probers
- HA7200 · MEMS manufacturing equipment
- HA7300 · MEMS manufacturing equipment
- M4173 · Test handlers
Sources
Last updated: October 23, 2026